1. Field of the Invention
The present invention relates to semiconductor interposers and package structures having the same, and more particularly, to a semiconductor interposer having a UBM (Under Bump Metallurgy) layer and a package structure having the semiconductor interposer.
2. Description of Related Art
Flip-chip technologies facilitate to reduce chip packaging sizes and shorten signal transmission paths and therefore have been widely used for chip packaging. Various types of packages such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages can be achieved through flip-chip technologies.
In a flip-chip packaging process, a big CTE (Coefficient of Thermal Expansion) mismatch between a chip and a packaging substrate adversely affects the formation of joints between conductive bumps of the chip and contacts of the packaging substrate, thus easily resulting in delamination of the conductive bumps from the packaging substrate. On the other hand, along with increased integration of integrated circuits, the CIE mismatch between the chip and the packaging substrate induces more thermal stresses and leads to more serious warpage, thereby reducing the product reliability and resulting in failure of a reliability test.
Accordingly, a silicon interposer is disposed between the packaging substrate and the semiconductor chip. Since the silicon interposer is close in material to the semiconductor chip, the above-described drawbacks caused by a CTE mismatch can be effectively overcome.
FIG. 1 is a schematic cross-sectional view of a conventional package structure having a silicon interposer. Such a package structure overcomes the above-described drawbacks. In addition, compared with a package structure having a semiconductor chip directly disposed on a packaging substrate, the package structure of FIG. 1 has a reduced layout area.
For example, a packaging substrate generally has a minimum line width/pitch of 12/12 um. When the I/O count of a semiconductor chip increases, since the line width/pitch of the packaging substrate cannot be reduced, the area of the packaging substrate must be increased such that more circuits can be formed on the packaging substrate and electrically connected to the semiconductor chip having high I/O count. On the other hand, referring to FIG. 1, a plurality of semiconductor chips 11 are disposed on a silicon interposer 12 having through silicon vias (TSVs) and the silicon interposer 12 is further disposed on a packaging substrate 13. As such, the semiconductor chips 11 are electrically connected to the packaging substrate 13 through the silicon interposer 12. Through a semiconductor process, the silicon interposer 12 can have a line width/pitch of 3/3 um or less. Therefore, the semiconductor chips 11 having high I/O counts can be disposed on the through silicon interposer 2 without the need to increase the area of the packaging substrate 13. Further, the fine line width/pitch of the silicon interposer 12 facilitates to shorten the electrical transmission path. Therefore, compared with semiconductor chips directly disposed on a packaging substrate, the semiconductor chips 11 disposed on the silicon interposer 12 can achieve a higher electrical transmission speed (efficiency).
To meet the miniaturization requirement of electronic products, the silicon interposer 12 of the above-described package structure is becoming lighter, thinner, shorter and smaller. Generally, the silicon interposer 12 has a thickness below 100 um, for example, in a range of 50 to 100 um. However, such a small thickness easily leads to warping of the silicon interposer 12 during fabrication of the silicon interposer 12, when the semiconductor chips 11 are disposed on the silicon interposer 12 or when the silicon interposer 12 is disposed on the packaging substrate 13, thereby generating large stresses on conductive elements 14 (such as u-bumps) between the semiconductor chips 11 and the silicon interposer 12 or conductive elements 15 (such as c4 bumps) between the silicon interposer 12 and the packaging substrate 13 and hence easily causing cracking of the joints.
Particularly, serious cracking often occurs to the conductive elements 14. In addition, when processes such as chip mounting processes or heating processes are performed after singulation of the silicon interposer 12, large stresses easily occur around a periphery of the silicon interposer 12, which easily cause warping of the silicon interposer 12 and consequently reduce the reliability of final products.
Therefore, how to overcome the above-described drawbacks has become critical.